1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a stacked structure.
2. Description of the Related Art
Electrically erasable programmable nonvolatile memories include a flash memory as well known in the art, which comprises a memory cell array of NAND-connected or NOR-connected memory cells having a floating gate structure. A ferroelectric memory is also known as a nonvolatile fast random access memory.
On the other hand, technologies of pattering memory cells much finer include a resistive memory, which uses a variable resistive element in a memory cell as proposed. Known examples of the resistive element include a phase change memory element that varies the resistance in accordance with the variation in crystal/amorphous states of a chalcogenide compound; an MRAM element that uses a variation in resistance due to the tunnel magneto-resistance effect; a polymer ferroelectric RAM (PFRAM) memory element including resistors formed of a conductive polymer; and a memory element that causes a variation in resistance on electrical pulse application (Patent Document 1: JP 2006-344349A, paragraph 0021).
The resistive memory may configure a memory cell with a serial circuit of a Schottky diode and a variable resistive element in place of the transistor. Accordingly, it can be stacked easier and three-dimensionally structured to achieve much higher integration advantageously (Patent Document 2: JP 2005-522045A).
Many of the semiconductor memory devices having such the stacked structure include a contact plug for connecting a line in a certain memory layer to a line in a different memory layer. Further, at an end of the line in each memory layer, a contact connector is formed for connection to the contact plug. Therefore, there is a need for providing space for formation of the contact plug and the contact connector, which not only results in an increase in chip area but also, depending on the connection state, causes variations in electrical property among lines in the memory layers as a problem.